Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, flash drives, digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.
Flash memory density has increased and cost per bit has decreased in recent years. To increase density, memory cell size and proximity to adjacent memory cells have been reduced. This can lead to problems with disturb conditions resulting from interaction between adjacent memory cells. Additionally, flash memory is still relatively slow when compared to other forms of memory (e.g., DRAM).
Variable resistance memory, such as resistive random access memory (RRAM), is a memory technology that provides a non-volatile memory function in a variable resistance memory cell. For example, a low resistance of the memory cell indicates one state while a high resistance indicates a second state. Examples of such variable resistance memory includes metal oxide, phase change (GST), nano-filament, stiction force, mechanical deformation, polymer, molecular, conductive bridge, and MRAM.
FIG. 1 shows a typical cross point resistive RAM array, with a select device and a programmable element in series forming each cell at an intersection of a pair of access lines, which are referred to herein as bit lines and word lines, but which for the purposes of a RRAM are interchangeable. The select device is a non-ohmic device, such as a diode. A typical core cell size for RRAM cells is 4F2. That is, with F as the smallest feature size, the area of an RRAM cell on a die, including any overhead and spacing, is 2F by 2F, or 4F2.
Because of the size of modern arrays, the amount of current from a large amount of cells connected to an access line, and leakage from cells, bit lines and word lines cannot span an entire length and width of a memory. Connected to in this context includes, but is not limited to, being electrically connected to, whether directly or indirectly through an intervening component or components. Therefore, bit line and word line segmentation is used as is shown in FIG. 2. For segmenting bit lines or word lines, segmentation transistors such as transistors 202 are used. The segmentation transistors 202 are used to divide the array into smaller sections. It is difficult to fabricate small transistors, and it is difficult to tightly pack transistors. Further, as cells continue to scale smaller and smaller, transistors do not become smaller at the same rate. Segmentation transistors such as transistors 202 are far larger than the 4F2 size of typical RRAM cells, and as the density of arrays continues to increase, large segmentation transistors take up an increasing percentage of die space, reducing efficiency of the array.
For the reasons stated above, and for other reasons stated below that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an improved memory array architecture.